EENG 326 DIGITAL SYSTEMS DESIGN II

DIGITAL SYSTEMS
DESIGN II
EENG 326
LECTURER: ING. LEONARD YOMMIE SESAY
Phone: +23276413865
E-mail: [email protected]
EENG 326 DIGITAL SYSTEMS DESIGN II

MULTIVIBRATOR
Multivibrators are classified according to number of stable states of the circuit. There are three types of multivibrators
namely:
1. Monostable
2. Bistable
3. Astable
MONOSTABLE MULTIVIBRATOR or ONE-SHORT MULTIVIBRATOR
This have one stable state and one unstable state normally it’s rest in its stable state but can be switch to the other state by
applying an external trigger pulse. It stays in the unstable for a certain time before returning to it stable states. It converts a
pulse of unpredictable length form a switch into a square wave pulse of predictable length and height (Voltage). The width
(time) of the output pulse is usually determine by the resistance and capacitance value in an RC circuit or network called
timing circuit connected to the device.
Re-triggerable and non-re-triggerable monostable multivibrators.
A re-triggerable monostable is one that will accept a new trigger input while the output pulse is still in progress. The new
trigger initiates a new timing cycle, so the pulse is extended beginning where the new trigger occurs, a length of time
required to the monostable full output pulse width. In order word regardless of how long an output pulse have been high. A
new trigger input effectively restart time and super impose a new pulse beginning where the trigger occurs.

Non-re-triggerable monostable simply ignore any new trigger that occurs while a pulse output is in progress.
Waveform comparison of non-re-triggerable and re-triggerable monostable multivibrators.
EENG 326 DIGITAL SYSTEMS DESIGN II
EENG 326 DIGITAL SYSTEMS DESIGN II

MONOSTABLE MULTIVIBRATOR FROM IC SN74121

A widely use integrated circuit version of a non-re-triggerable IC is from the IC SN74121 TTL family. The figure below
shows the wring of the SN74121 with the connection.
EENG 326 DIGITAL SYSTEMS DESIGN II

Truth Table

Where L=low, H=high, X = Don’t care

From the truth table we can see that it can be triggered or fired if A1 or A2 is low, and B goes from low-to-high or B is high
and A1 or A2 goes from high-to-low.
The width of the output pulse produced by the 74121 is given by:
𝑷𝑾 = (𝐥𝐧𝟐)𝑹𝒆𝒙𝒕 𝑪𝒆𝒙𝒕 = 𝟎. 𝟔𝟗𝑹𝒆𝒙𝒕 𝑪𝒆𝒙𝒕 … … . . (𝒊)

A variation in output pulse width due to failure of all pulses to return low in the same time interval is called trailing-edge
jitter.
To prevent trailing edge jitter in the 741211 the external timing components must be in the range:
1.4𝑘Ω < 𝑅𝑒𝑥𝑡 < 40𝑘Ω
1.0𝑝𝐹 < 𝐶𝑒𝑥𝑡 < 1000𝜇𝐹
EENG 326 DIGITAL SYSTEMS DESIGN II

CLASSWORK SET
1. a. A 74121 have external resistance 𝑅𝑒𝑥𝑡 = 14.43𝑘Ω and the external capacitance 𝐶𝑒𝑥𝑡 = 1𝑢𝐹. What is the size of
the pulse width?
b. To what value would 𝐶𝑒𝑥𝑡 be changed if it is desired to reduce the pulse width to 7.5𝑚𝑠?

Application of Monostable Multivibrator

1. Switch Denouncer (Read on)
2. Gating: in many digital systems it is necessary to enable gates (logic) to permit the passage of digital signals to
another part of the system for a prescribed period.
3. Time Delays: Monostable are widely used to deliver pulse a certain time after the occurrence of another pulse to
create a prescribed time delay in the delivery of a pulse.
4. Synchronization: Digital computer operations are often synchronized by sequences of pulses that occur on different
control lines at different times. It is used in detection of a missing pulse.
EENG 326 DIGITAL SYSTEMS DESIGN II

ASTABLE OR FREE-RUNNING MULTIVIBRATORS

Astable means not stable and has no stable states it switches from one state to the other order automatically at a rate
determined by the circuit component. Consequently, like an oscillator it generates a continuous steam of square red pulse.
One of the important uses of a stable Multivibrator is to produce timing pulses for keeping the different parts of a digital
system such as a computer.
555 TIMERS
This is a widely used integrated circuit having considerable versatility. It can be operated as a Monostable or as an Astable
Multivibrator as well as perform many other specific functions.
EENG 326 DIGITAL SYSTEMS DESIGN II

The principal components of the circuit are:

• 2 voltage comparators,
• A flip flops.
• And a transistor.
2 1 2
Only the 𝑄̅ output of the flip flop is used. The 5𝑘Ω resistor string provides 2 reference voltages 𝑉𝑐𝑐 𝑎𝑛𝑑 𝑉𝑐𝑐 , the 𝑉 for
3 3 3 𝑐𝑐
1
comparator A and 𝑉𝑐𝑐 for comparator B.
3
The output of either comparator is a logic 1 whenever its upper input is at a higher voltage than the lower input.

STABLE STATE
• In the stable state (no pulse output) the trigger input (pin 2) is held high typically at 𝑉𝑐𝑐 , so the output of the trigger
comparator B Is low (0). The flipflop is in the reset state, 𝑄̅ is High (1), i.e., the output (pin3) is low.
• The high voltage 𝑄 ̅ is applied to the base of the transistor keeps it on i.e., conducting like a closed switch. The closed
switch short circuits the external capacitor so it cannot charge.
• Since the voltage across the capacitor is low (0) and the output of the threshold comparator is low (0). thus, both set
and reset input of the flipflop are low in stable state.
• To trigger the output pulse a negative going pulse is applied to the trigger input.
EENG 326 DIGITAL SYSTEMS DESIGN II

555 timer as MONOSTABLE MULTIVIBRATOR

1
• When the negative trigger input falls below 𝑉𝑐𝑐 , the output of trigger comparator B goes high (on).
3
• The low to high transition sets the flipflop, which makes 𝑄 ̅ go low.
• The output at pin 3 is then the leading edge of the output pulse.
• The low 𝑄̅ turns of the discharged transistor, so it is like an open switch then the external capacitor C begins to charge
through R.
EENG 326 DIGITAL SYSTEMS DESIGN II

2
• When the capacitor voltage rises above 𝑉𝑐𝑐 , the output of threshold comparator A goes High, this low to high
3
̅
transition resets the flipflop and 𝑄 goes high then the output at pin 3 goes low. The high voltage at the base of the
discharge transistor turns it on again and the capacitor will discharge through the transistor.
EENG 326 DIGITAL SYSTEMS DESIGN II

Note: the external capacitor C charges according to

−𝒕
𝑽𝒄 (𝒕) = 𝑽𝒄𝒄 (𝟏 − 𝒆𝑹𝑪 ) 𝒗𝒐𝒍𝒕𝒔 … … … … (𝟐)
2 2
The output pulse has a width (𝑃𝑊 ) equal to the time required for 𝑉𝑐 (𝑡) to rise from 0𝑣 𝑡𝑜 𝑉𝑐𝑐 𝑣𝑜𝑙𝑡𝑠. Setting 𝑉𝑐 (𝑡) = 𝑉
3 3 𝑐𝑐
and 𝑡 = 𝑝𝑤 yileds,
𝟐 −𝑷𝑾
𝑽𝒄𝒄 = 𝑽𝒄𝒄 (𝟏 − 𝒆 𝑹𝑪 )
𝟑
𝟐 −𝑷𝑾 𝟏 −𝑷𝑾
= 𝟏 − 𝒆 𝑹𝑪 => = 𝒆 𝑹𝑪
𝟑 𝟑
Taking ln on both sides produces
𝑷𝑾 𝟏
= −𝐥𝐧 ( )
𝑹𝑪 𝟑
𝟏
𝑷𝑾 = −𝑹𝑪𝒍𝒏( )
𝟑
𝑷𝑾 = 𝑹𝑪𝒍𝒏𝟑
𝑷𝑾 ≅ 𝟏. 𝟏𝑹𝑪 secs
𝑷𝑾
𝑹=
𝑪
EENG 326 DIGITAL SYSTEMS DESIGN II

𝑷𝑾
𝑪=
𝑹
𝑻𝒐𝒏
DUTY CYCLE, 𝑫𝑪 =
𝑻𝒐𝒏 + 𝑻𝒐𝒇𝒇

𝑻𝒐𝒏
𝑫𝑪 =
𝑻
𝟏
𝑫𝑪 = .𝑻
𝑻 𝒐𝒏
𝑫𝑪 = 𝑭𝑷𝑾
𝑫𝑪
𝒕𝒉𝒆𝒓𝒆𝒇𝒐𝒓𝒆 𝑷𝑾 =
𝑭
Where 𝑫𝑪 = 𝒅𝒖𝒕𝒚 𝒄𝒚𝒄𝒍𝒆 𝒂𝒏𝒅 𝑭 = 𝑭𝒓𝒆𝒒𝒖𝒆𝒏𝒄𝒚
EENG 326 DIGITAL SYSTEMS DESIGN II

CLASSWORK SET
1. A 1𝐾𝐻𝑍 square wave is applied to the trigger of 555 monostable multivibrator of 𝐶 = 0.1𝜇𝐹. What should be the
value R if the output is to have 75% 𝑑𝑢𝑡𝑦 𝑐𝑦𝑐𝑙𝑒?
2. Design a monostable multivibrator using a 555 timer that produce a 1sec wide open pulse.
3. The trigger input of a 555 timer operates as a monostable shown below. If the externally timing components are 𝑅 =
4.7𝐾Ω 𝑎𝑛𝑑 𝐶 = 0.1𝜇𝐹. What is the Duty Cycle of the output of the 555 timer?
Draw a timing diagram showing the trigger input and the 555-output trigger.
EENG 326 DIGITAL SYSTEMS DESIGN II

555 TIMER AS ASTABLE MULTIVIBRATOR

Here there is a R2 connected between the capacitor and the discharge transistor to slow the discharge. The capacitor charges
2
through R1 and R2 until it reaches 𝑉𝑐𝑐 , at that time the threshold comparator A reset the flip flop. The High at 𝑄̅ turns on
3
1
the discharge transistor and the capacitor discharge through R2 only. When the capacitor voltage falls below 𝑉𝑐𝑐 , the
3
̅
trigger comparator set the flip flop, 𝑄 goes low then the discharge transistor goes off, and the cycle start’s over again.
EENG 326 DIGITAL SYSTEMS DESIGN II

Typical waveform is shown below for an Astable multivibrator.

EENG 326 DIGITAL SYSTEMS DESIGN II

The capacitor discharge through R2 only

2
the discharge equation staring at 𝑉𝑐𝑐 , is given by.
3
−𝑡
2
𝑉𝑐 (𝑡) = 𝑉 𝑒 𝑅2 𝐶
3 𝐶𝐶
1
The capacitor discharges to 𝑉𝑐𝑐 at time 𝑇2 of the discharge time.
3
1
Setting, 𝑉𝑐 (𝑡) = 𝑉 at = T2
3 𝐶𝐶
1 2 −𝑇2
𝑉 = 𝑉𝐶𝐶 𝑒 2𝐶
𝑅
3 𝐶𝐶 3
1 −𝑇2
= 𝑒 2𝐶
𝑅
2
𝟏
𝑻𝟐 = −𝑹𝟐 𝑪𝒍𝒏( )
𝟐
𝑻𝟐 = 𝑹𝟐 𝑪𝒍𝒏(𝟐)

Hence, 𝑻𝒅𝒊𝒔𝒄𝒉𝒂𝒓𝒈𝒆 = 𝑻𝒐𝒇𝒇 = 𝑻𝟐 = 𝟎. 𝟔𝟗𝟑𝑹𝟐 𝑪

1
During charging, the capacitor starts at 𝑉𝐶𝐶 and charge towards𝑉𝐶𝐶 through R1 and R2.
3
EENG 326 DIGITAL SYSTEMS DESIGN II

The charging equation is

2 −𝑡
𝑽𝒄 (𝒕) = 𝑽𝒄𝒄 − 𝑉𝐶𝐶 𝑒 (𝑅1 + 𝑅2 )𝐶
3
2 2
The time 𝑇1 for the capacitor to charge to 𝑉𝐶𝐶 is found by setting 𝑽𝒄 (𝒕) = 𝑉 and 𝑡 = 𝑇1
3 3 𝐶𝐶

2 2 −𝑇1
𝑉 = 𝑽𝒄𝒄 − 𝑽𝒄𝒄 𝑒 + 𝑅2)𝐶
(𝑅1
3 𝐶𝐶 3
1 −𝑇1
= 𝑒 + 𝑅2)𝐶
(𝑅1
2
𝑇𝑐ℎ𝑎𝑟𝑔𝑒 = 𝑇𝑂𝑁 = 𝑇1 = (𝑅1 + 𝑅2 )𝐶𝑙𝑛2

𝑻𝟏 = 𝟎. 𝟔𝟗𝟑(𝑹𝟏 + 𝑹𝟐 )𝑪
The Total period of oscillation is
𝑇 = 𝑇1 + 𝑇2 = 0.693𝑅2 𝐶 + 0.693(𝑅1 + 𝑅2 )𝐶
𝑻 = 𝟎. 𝟔𝟗𝟑(𝑹𝟏 𝑪 + 𝟐𝑹𝟐 𝑪)
1 1
𝐹𝑟𝑒𝑞𝑢𝑒𝑛𝑐𝑦, 𝐹 = =
𝑇 𝟎. 𝟔𝟗𝟑(𝑹𝟏 𝑪 + 𝟐𝑹𝟐 𝑪)
𝟏. 𝟒𝟒
𝑭= 𝑯𝒁
(𝑹𝟏 𝑪 + 𝟐𝑹𝟐 𝑪)
EENG 326 DIGITAL SYSTEMS DESIGN II

𝑇1
Duty Cycle, DC =
𝑇1 + 𝑇2

𝑹𝟏 + 𝑹𝟐
𝑫𝑪 =
𝑹𝟏 + 𝟐𝑹𝟐
𝐼𝑓 𝑅1 = 𝑅2 = 𝑅
𝟐𝑹
𝑫𝑪 = = 𝟎. 𝟔𝟔𝟕
𝟑𝑹
Frequency in terms of Duty Cycle
𝟏
𝑭=
𝒍𝒏𝟐(𝑹𝟏 + 𝟐𝑹𝟐 )𝑪
𝟏
𝑭=
𝟑𝑹𝑪𝒍𝒏𝟐
Note that the duty cycle must always be greater than 0.5 because the capacitor takes longer to charge and discharge.
EENG 326 DIGITAL SYSTEMS DESIGN II

CLASSWORK SET
1.
a. Design an Astable 555 Circuit to produce a 20 kHz waveform with a 75% duty Cycle.
b. Sketch the waveform.
c. What will be the frequency and duty cycle of the output of the 555 timer in (a) if the resistors value is
interchanged?
2. Given the following 555 Timer in astable mode where 𝑅1 = 50𝐾Ω , 𝑅2 = 10𝐾Ω 𝑎𝑛𝑑 𝐶 = 0.001𝑢𝐹, 𝑉𝑐𝑐 = 6𝑣

a. Calculate the on time of the multivibrator.

b. Calculate the off time of the multivibrator.
c. Calculate the frequency and the period of the multivibrator.
d. Derive an expression which relates duty cycle of the output to the values of R1 and R2. Do no Substitute in
the values.
EENG 326 DIGITAL SYSTEMS DESIGN II

e. Using the equation you have found in (d), determine the approximate duty cycle of the circuit when.
i. 𝑅1 𝑖𝑠 𝑓𝑎𝑟 𝑔𝑟𝑒𝑎𝑡𝑒𝑟 𝑡ℎ𝑎𝑛 𝑅2.( R1 >> R2 )
ii. 𝑅1 𝑖𝑠 𝑓𝑎𝑟 𝑔𝑟𝑒𝑎𝑡𝑒𝑟 𝑡ℎ𝑎𝑛 𝑅2 (𝑅1 = 𝑅2 ) .
iii. 𝑅1 𝑖𝑠 𝑓𝑎𝑟 𝑙𝑒𝑠𝑠 𝑡ℎ𝑎𝑛 𝑅2 . (𝑅1 ≪ 𝑅2 )
f. What are the minimum and maximum voltages across the capacitor?
g. List two ways you could change components in the circuit to double the frequency of the output pulses. Then,
demonstrate mathematically that your component changes have had the desired effect. 𝑅1 , 𝑅2 , & 𝐶.
h. As 𝑉𝑐𝑐 increase does the charge time increase or decrease or stay the same? Why?
i. Does the frequency of the output pulse increase or decrease as the input voltage increase? Why?
3.
a. Design an astable multivibrator shown above using 𝑅1 , 𝑅2 , & 𝐶. The output should have a frequency, 𝐹 = 5𝐾𝐻𝑍
and Duty Cycle of 60%.
b. Sketch to scale the 555 timer output using values on the x-axis(time) for rise and fall of the pulse ie 𝑇1 𝑎𝑛𝑑 𝑇2 . Also
indicate the amplitude (Voltage) on the y-axis.

4. Design an astable multivibrator with a free running frequency of 1.5KHZ and a Duty Cycle of 3:4. Use a 0.1𝜇𝐹
timing capacitor.
EENG 326 DIGITAL SYSTEMS DESIGN II

SCHMITT TRIGGER
Sometimes an input signal to a digital circuit does not directly fit the distribution of digital signal for various reasons, it may have slow raise and or
slow falling times or may have acquire some noise that will be sense by other circuitry. This condition and many others required a specialize circuit that
will clean-up a signal and forces it to true digital shape. The required circuit is called a Schmitt Trigger.
The symbol is like a NAND gate with a Hysteresis.

+ −
A Schmitt operate like a voltage comparator, except that the value (𝑒𝑖𝑛 − 𝑒𝑖𝑛 ) that causes the output to switch from low to high is different from the
value that causes to switch from high to low. Thus, there is a range of value between low and high switching levels where no switching occurs. This is
called the HYSTERESIS of the Schmitt trigger.
EENG 326 DIGITAL SYSTEMS DESIGN II

CHARACTERISTICS OF SCHMITT TRIGGER

UTP = upper trip point

LTP = lower trip point
𝐻𝑦𝑠𝑡𝑒𝑟𝑒𝑠𝑖𝑠 𝑅𝑎𝑛𝑔𝑒 = 𝑈𝑇𝑃 – 𝐿𝑇𝑃 …………………1

TYPES OF SCHMITT TRIGGER

1. Inverting Schmitt Trigger
2. Non-Inverting Schmitt Trigger
EENG 326 DIGITAL SYSTEMS DESIGN II

INVERTING SCHMITT TRIGGER

𝑹𝟐 𝑹𝟏
𝑳𝑻𝑷 = × 𝑽𝑹𝒆𝒇 + × 𝑽𝑳𝑶
𝑹𝟏 + 𝑹𝟐 𝑹𝟏 + 𝑹𝟐
𝑹𝟐 𝑹𝟏
𝑼𝑻𝑷 = × 𝑽𝑹𝒆𝒇 + × 𝑽𝑯𝑳
𝑹𝟏 + 𝑹𝟐 𝑹𝟏 + 𝑹𝟐
𝑯𝒚𝒔𝒕𝒆𝒓𝒆𝒔𝒊𝒔 𝑹𝒂𝒏𝒈𝒆 = 𝑼𝑻𝑷 − 𝑳𝑻𝑷
𝑹𝟐
𝑯𝒚𝒔𝒕𝒆𝒓𝒆𝒔𝒊𝒔 𝑹𝒂𝒏𝒈𝒆 = ( ) (𝑽𝑯𝑳 − 𝑽𝑳𝑶 )
𝑹𝟏 + 𝑹𝟐
EENG 326 DIGITAL SYSTEMS DESIGN II

CLASSWORK SET
1. Sketch the output of the Schmitt trigger shown below:
(a) Assume 𝑽𝑳𝑶 = −𝟓𝑽, 𝑽𝑯𝑳 = +𝟓𝑽, 𝑽𝑹𝒆𝒇 = 𝟑𝑽
(b) Assume 𝑽𝑳𝑶 = 𝟎𝑽, 𝑽𝑯𝑳 = +𝟓𝑽, 𝑽𝑹𝒆𝒇 = 𝟑𝑽
(c) Assume 𝑽𝑳𝑶 = −𝟓𝑽, 𝑽𝑯𝑳 = +𝟓𝑽, 𝑽𝑹𝒆𝒇 = 𝟎𝑽
Find the hysteresis in each case.
EENG 326 DIGITAL SYSTEMS DESIGN II
EENG 326 DIGITAL SYSTEMS DESIGN II

NON-INVERTING SCHMITT TRIGGER

Hence the trigger levels can be found from

−𝑅1
𝐿𝑇𝑃 = × 𝑉𝐻𝐿
𝑅2
𝑅1
𝑈𝑇𝑃 = × |𝑉𝐿𝑂 |
𝑅2
𝑊ℎ𝑒𝑟𝑒 |𝑉𝐿𝑂 | 𝑖𝑠 𝑡ℎ𝑒 𝑎𝑏𝑠𝑜𝑙𝑢𝑡𝑒 𝑣𝑎𝑙𝑢𝑒 𝑜𝑓 𝑉𝐶𝐶

CLASSWORK SET

Q) A voltage comparator has a 𝑉𝐿𝑂 = −10𝑉 𝑎𝑛𝑑 𝑉𝐻𝐿 = +10𝑉

a. Design a non-inverting Schmitt Trigger that has a lower-level trigger level 𝐿𝑇𝑃 = −4𝑉 𝑎𝑛𝑑 𝑈𝑇𝑃 = +4𝑉
b. Sketch the output of the trigger when its input is 10V peak to peak sine wave.
EENG 326 DIGITAL SYSTEMS DESIGN II

APPLICATION OF SCHMITT TRIGGER

Because Schmitt trigger provides fast changing output in response to slowly changing input and because their hysteresis
improves noise immunity, are constructed in integrated circuit form for use with logic family circuitry.

1. RISE TIME IMPROVER

2. NOISE REMOVER
EENG 326 DIGITAL SYSTEMS DESIGN II

3. SWITCH DEBOUNCER

4. SQUARE WAVE OSCILLATOR

EENG 326 DIGITAL SYSTEMS DESIGN II

DIGITAL LOGIC-CIRCUIT FAMILY

Members of a logic family are made with the same technology having similar circuit structure and exhibited the same basic
features.

Family

The most popular logic family are the TTL(transistor-transistor logic), CMOS(Complementary metal oxide) and
ECL(Emitter Couple logic).
EENG 326 DIGITAL SYSTEMS DESIGN II

CHARACTERISTICS
The characteristics of various logic family can be classified under the following family:
• Propagation Delay (Speed of Delay),
• Noise Margin (Immunity),
• Power Dissipation,
• Fan-in and Fanout,
• Figure of Merit,
• Operating Temperature Range,
• Current and Voltage parameters
• Power supply requirement.
EENG 326 DIGITAL SYSTEMS DESIGN II

1. PROPAGATION DELAY
It is the time that elapse between the application of an input signal and the resulting change in the logic state at the output.
Generally, it is measured and the 50% point of the input and output wave form.
Consider an inverter circuit below.

The two delays: Low to high Propagation Delay (TPLH) and High to low Propagation Delay(TPHL) are not necessarily equals
1
to one and other. The inverter propagation Delay (𝑇𝑃 ) is define and the delay of the two quantities: 𝑇𝑃 = (𝑇𝑃𝐿𝐻 + 𝑇𝑃𝐻𝐿 ).
2
The shorter the propagation delays the higher the speed at which the logic family operates.
EENG 326 DIGITAL SYSTEMS DESIGN II

2. NOISE MARGIN OR NOISE IMMUNITY

The noise margin of a gate is the maximum noise voltage that can appear at it input terminal without causing a change
in the output state. That is the gate insensitivity to noise.
Consider an example of two cascaded NAND gate below:
EENG 326 DIGITAL SYSTEMS DESIGN II

The output voltage of a gate may vary between 𝑉𝑂𝐻𝑚𝑎𝑥 and 𝑉𝑂𝐻𝑚𝑖𝑛 for logic 1 output and between the
𝑉𝑂𝐻𝑚𝑎𝑥 and 𝑉𝑂𝐻𝑚𝑖𝑛 for the output to be logic 0. Similarly, the input voltage may vary between the limit 𝑉𝑖𝐻𝑚𝑎𝑥 and
𝑉𝑖𝐻𝑚𝑖𝑛 for input state to be at logic 1. For the input state to be at logic 0 the input voltage must be between the limits
𝑉𝑖𝐻𝑚𝑎𝑥 and 𝑉𝑖𝐻𝑚𝑖𝑛 .

𝑻𝒉𝒆 𝒍𝒐𝒘 − 𝒍𝒆𝒗𝒆𝒍 𝒏𝒐𝒊𝒔𝒆 𝒎𝒂𝒓𝒈𝒊𝒏 𝒊𝒔 𝒅𝒆𝒇𝒊𝒏𝒆𝒅 𝒃𝒚

𝑵𝑳 = 𝑽𝑰𝑳(𝒎𝒂𝒙) – 𝑽𝑶𝑳(𝒎𝒂𝒙)

𝑇ℎ𝑒 𝐻𝑖𝑔ℎ − 𝑙𝑒𝑣𝑒𝑙 𝑛𝑜𝑖𝑠𝑒 𝑚𝑎𝑟𝑔𝑖𝑛 𝑖𝑠 𝑑𝑒𝑓𝑖𝑛𝑒𝑑 𝑏𝑦

𝑵𝑯 = 𝑽𝑶𝑳(𝒎𝒊𝒏) – 𝑽𝑰𝑯(𝒎𝒊𝒏)

When noise margin is quoted in manufacturer data sheet it is usual to give the worst case the robustness of a logic family is
determine by its ability to reject noise.
EENG 326 DIGITAL SYSTEMS DESIGN II

3. POWER DISSIPATION
The DC power Dissipated of a gate is the product of the DC supply voltage and the mean current taken from the supply.
So, this power is the static power.
𝑆𝑡𝑎𝑡𝑖𝑐 𝑃𝑜𝑤𝑒𝑟 = 𝑃𝑠 = 𝑉𝐶𝐶 𝐼𝐶𝐶
The dynamic power of a gate is given by.
𝑃𝐷 = 𝐹𝐶𝑉 2
𝐶 = 𝐶𝐿 + 𝐶𝑃𝐷
Where 𝐶𝐿 = Load capacitance
𝐶𝑃𝐷 = 𝐼𝑛𝑡𝑒𝑟𝑛𝑎𝑙 𝑝𝑜𝑤𝑒𝑟 𝑑𝑖𝑠𝑠𝑖𝑝𝑎𝑡𝑖𝑜𝑛 𝑐𝑎𝑝𝑎𝑐𝑖𝑡𝑎𝑛𝑐𝑒
𝑇𝑜𝑡𝑎𝑙 𝑃𝑜𝑤𝑒𝑟 = 𝑃 = 𝑃𝑠 + 𝑃𝐷
𝐶𝐿𝐴𝑆𝑆𝑊𝑂𝑅𝐾 𝑆𝐸𝑇
1. A 74HCO2 quad 2-input NOR gate is operated at room temperature with 4.5V supply voltage. The total dc current drawn
from the supply is 15uA. Each NOR gate drives another gate whose input capacitance is 6pf, and each is driven by a
1MHz square wave. Find the total power dissipation of the circuit if the power dissipation capacitance is 22pF per gate.
EENG 326 DIGITAL SYSTEMS DESIGN II

4. FAN-IN & FAN-OUT

FAN-IN: fan-in of a gate is the number of inputs connected to the gate.
FAN-OUT (also called loading factor) – it is the number of gate input that can be connected into a single gate output
without overloading the output gate.

𝐼𝑂𝐿 (𝑚𝑎𝑥)
𝐹𝐴𝑁 − 𝑂𝑈𝑇(𝐿𝑂𝑊) =
𝐼𝐼𝐿 (𝑚𝑎𝑥)
𝐼𝑂𝐻 (𝑚𝑎𝑥)
𝐹𝐴𝑁 − 𝑂𝑈𝑇(𝐻𝐼𝐺𝐻) =
𝐼𝐿𝐻 (𝑚𝑎𝑥)
NOTE: Fan-out is chosen as the smaller of the worst case.
EENG 326 DIGITAL SYSTEMS DESIGN II

5. FIGURE OF MERIT
Figure of Merit: It is the product of speed and average power consumption per logic gate. In other words, it is the
product of the propagation delay and the power dissipated. The smaller the value the better the overall performance.
𝑭𝒊𝒈𝒖𝒓𝒆 𝒐𝒇 𝒎𝒆𝒓𝒊𝒕 = 𝒑𝒓𝒐𝒑𝒂𝒈𝒂𝒕𝒊𝒐𝒏 𝒅𝒆𝒍𝒂𝒚 × 𝑷𝒐𝒘𝒆𝒓

CURRENT SINKING & CURRENT SOURCING

A current sink is a circuit that is supplied with a current by another circuit, whiles a current source supplies a current to a
sink load.
EENG 326 DIGITAL SYSTEMS DESIGN II

(a) and (c) are current sink, and (b) and (d) are current sources.

In (a) current will flow into the sink circuit when the switch is closed. While in (b) current will flow out of the source
circuit.

TRANSISTOR-TRANSISTOR LOGIC OR TTL FAMILY

The most popular and widely used logic family is the TTL family.

Advantages
1. High speed
2. Good fan-in and fan-out
3. Easily interface with another digital circuitry
4. Relatively Cheap
5. Readily available from several sources and in many versions

Disadvantages
1. Poor noise immunity
2. High power dissipation
EENG 326 DIGITAL SYSTEMS DESIGN II

TTL TYPES
1. Standard TTL – 74/75 series
• Wider temperature and voltages range
2. High Speed TTL -74H/54H source
• High speed, very high-power consumption
3. Low-power TTL – 54L series
• Low-power consumption but less speed
4. Schottky TTL
• High speed but high-power consumption

5. Low-power Schottky TTL -74L series

• Good speed, low power, and high frequency
6. Advance Schottky TTL – 74As series
7. Advance Low-power Schottky TTL – 74ALS series
8. Fast TTL – 74 F Series
EENG 326 DIGITAL SYSTEMS DESIGN II

ASSIGNMENT
Write the difference between high speed TTL and Low power TTL.

FLOATING POINT
The input to a logic gate should not be left unconnected i.e. floating. Since its apparent voltage might not be the one
expected.
For example, A floating input in a NOR gate behave as if it where Low, while in a NAND gate it acts as if it were High. So,
in practice depending on the voltage level required and input should be connected to 𝑒𝑖𝑡ℎ𝑒𝑟 + 𝑉𝐶𝐶 𝑜𝑟 𝑡𝑜 0𝑉.

PRACTICAL POINT FOR TTL.

1. Unused input behaves as if they are connected to 5V.
2. Fan-out of TTL IC is 100.
3. The 5V power supply used for TTL IC should be well regulated and adequately decoupled to deal with the brief but large
current spikes which occur when IC switch from one sate to another.
EENG 326 DIGITAL SYSTEMS DESIGN II

TTL INVERTERS
EENG 326 DIGITAL SYSTEMS DESIGN II

When the input is high the base to the emitter, The collector to emitter switch closes. The output is then 0v or low. When the
input is low the switch is open negligible or no voltage drop across the collector resistor RC, the output is High(𝑉𝐶𝐶 )
Logic Truth table
Input Output
1 0
0 1
EENG 326 DIGITAL SYSTEMS DESIGN II

TTL NAND GATE

A simplified circuit of a two-input NAND gate is shown below, but the fan-in may be up to eight (8).
EENG 326 DIGITAL SYSTEMS DESIGN II

Truth Table
A B Tr1 Tr2 X
L L ON OFF H
L H ON OFF H
H L ON OFF H
H H OFF ON L

With the bias resistor 𝑅1 , 𝑇𝑟1 acts as an AND gate whose output provides the input to the inverting output transistor, 𝑇𝑟2 . If
both input to Tr1 is high example high volt, no current flow from the base to the emitter since they are not forward bias i.e
Diodes 1 and 2 do not conduct.
However current flow through 𝑅1 and the base-collector junction of 𝑇𝑟1 i.e 𝐷3 conduct and then to ground Via 𝑇𝑟2 . This
current is high enough to saturate𝑇𝑟2 making the resistance of 𝑇𝑟2 very small compared to its load 𝑅2 . Therefore, the output
voltage is thus low(0v).

If either or both in input to 𝑇𝑟1 are low sufficient base current flows through 𝑅1 and the base emitter junction of 𝑇𝑟1 to cause
transistor action 𝐷1 𝑎𝑛𝑑/𝑜𝑟 𝐷2 conducts. As a result, 𝑇𝑟1 passes a large collector current to ground in the form of positive
charge stored in the P-type base of Tr2 which goes negative. 𝑇𝑟2 switches off i.e its resistance is very high, and the high
output voltage and a high output voltage is obtained. In summary the circuit act as a NAND gate since the output is high
unless both input is high.
EENG 326 DIGITAL SYSTEMS DESIGN II

CMOS COMPLEMENTARY METAL OXIDE SEMI CONDUCTOR FAMILY

CMOS is also called the ideal technology.

Advantages
1. Low power dissipation
2. High noise immunity
3. Large voltage tolerance

Disadvantages
1. Long propagation delay
2. Low output current capability

What are the precautions to be taken when handling MOS devices?

• Individuals handling MOSFET devices, and the workplace should be grounded.
• When a chip is out of circuit, it should be inserted in a special conductive foam that effectively short all pins together.
• In system design all unuse pin should be connected to ground or the supply voltage
• Circuit should have power applied before connecting or disconnecting low impedance signal such as false generator.
EENG 326 DIGITAL SYSTEMS DESIGN II

BASIC CMOS INVERTER CIRCUIT

NMOS and PMOS transistors are used together in a complementary way to form CMOS logic as
EENG 326 DIGITAL SYSTEMS DESIGN II

TRUTH TABLE

Vin Q1 Q2 Vout
0.0 ON OFF 5V
5 OFF ON 0V

When 𝑉𝑖𝑛 is at 0V, the lower NMOS 𝑄2 is off since its 𝑉𝐺𝑆 is 0V, but the upper PMOS is on since 𝑉𝐺𝑆 will be -5V. 𝑄2 is open
circuit, and Q1 is short circuited thus 𝑉𝑜𝑢𝑡 is equal to 5v. When 𝑉𝑖𝑛 is 5V, Q2 is short circuited and Q1 open thus 𝑉𝑜𝑢𝑡 is equal
0V, obviously circuit behaves as an inverter.
EENG 326 DIGITAL SYSTEMS DESIGN II

CMOS NAND GATE

The figure below shows a 2 input NAND Gate.
EENG 326 DIGITAL SYSTEMS DESIGN II

Truth Table
A B Q1 Q2 Q3 Q4 X
L L OFF OFF ON ON H
L H OFF ON ON OFF H
H L ON OFF OFF ON H
H H ON ON OFF OFF L

If either input is low the output X, is high if both inputs are high the output X, is low this is the operation required for the
circuit to function as a NAND Gate.
EENG 326 DIGITAL SYSTEMS DESIGN II

CMOS NOR GATE

A B Q1 Q2 Q3 Q4 X
L L OFF OFF ON ON H
L H OFF ON ON OFF L
H L ON OFF OFF ON L
H H ON ON OFF OFF L
A two input NOR gate is shown above. Only when A and B are low the output X is high and for all other combination of
inputs levels the output is low.
EENG 326 DIGITAL SYSTEMS DESIGN II

TYPES OF CMOS
i. 4000/14000 Series
ii. 74C – Series
iii. 74HC/HCT – series
iv. Advance CMOS 74AC/ACT
v. Advance high-speed CMOS 74AHC / 74AHCT
EENG 326 DIGITAL SYSTEMS DESIGN II

EMITTER COUPLED LOGIC

CHARACTERISTICS OF ECL
1. ECL is the fastest logic family.
2. It has an internal pull-down resistor connected between each input and the negative supply.
3. The differential input circuitry in ECL gate provides common mode rejection.
4. 4. The output impedance is desirable small
5. ECL gate has very large fan-out and relatively unaffected by capacitive loads
Advantages of ECL
1. High speed of operation
2. Moderate propagation delay
Disadvantages of ECL
1. Noise immunity is very very low
2. Consume much power
3. Low level of integration, not compatible to TTL and CMOS
Types of ECL
1. MC1600 series
2. MC1000 series
3. MC10H000 series
EENG 326 DIGITAL SYSTEMS DESIGN II

INTERFACING
The connection of ICs of 1 logic family to those of another to obtain the advantages of both is known as interfacing.
Methods used for CMOS and TTL interface.
Some of the methods used for CMOS to TTL interface are:
1. By using a CMOS buffer
2. By using supply voltage at 5v
3. By opening interface
4. By giving different supply voltages
Question
What is the necessity of interfacing in digital IC and what are the points to be kept in view while interfacing between TTL
and CMOS gate?
Ans
• To achieve the optimum performance in digital system, device from more than one family can be used which takes
advantage of the superior characteristics of each logic family. For example, CMOS logic IC’s can be used in those part
of the system where low power dissipation is required, and TTL be used where high speed of operation is required.
EENG 326 DIGITAL SYSTEMS DESIGN II

• When CMOS drives TTL the following conditions are required to be satisfied.
i. 𝑉𝑂𝐻 (𝐶𝑀𝑂𝑆) ≥ 𝑉𝑂𝐻 (𝑇𝑇𝐿)
ii. 𝑉𝑂𝐿 (𝐶𝑀𝑂𝑆) ≤ 𝑉𝐼𝐿 (𝑇𝑇𝐿)
iii. −𝐼𝑂𝐻 (𝐶𝑀𝑂𝑆) ≥ 𝑁𝐼𝐼𝐻 (𝑇𝑇𝐿)
iv. −𝐼𝑂𝐻 (𝐶𝑀𝑂𝑆) ≥ 𝑁𝐼𝐼𝐿 (𝑇𝑇𝐿)

CMOS to TTL Interfacing

Using Pull-up resistor
EENG 326 DIGITAL SYSTEMS DESIGN II

CMOS-TO-TTL INTERFACING USING CMOS BUFFER IC

EENG 326 DIGITAL SYSTEMS DESIGN II

Question
What is Tri-state logic and explain tri-state logic inverter with logic diagrams and truth table?
Ans
• In the tri-state logic, in addition to low impedance output 0 and 1, there is a third state known as the high impedance
state when the gate is disable it is in the third state.
Tri-state Logic inverter
The functional diagram of a tri-state is shown below.
EENG 326 DIGITAL SYSTEMS DESIGN II

Logic Diagram of Tri-state Logic inverter

When the control is low the drive is removed from T3 and T4. Hence both T3 and T4 are cut-off, and the output is in the third
state. When the control input is high the output Y is logic 1 or 0 depending on the data input. The truth table of the tri-state
logic inverter is given below.
EENG 326 DIGITAL SYSTEMS DESIGN II

TRUTH TABLE OF TRI-STATE LOGIC INVERTER

Data Controls Data

input output
0 0 High-Z
1 0 High- Z
0 1 1
1 1 0
EENG 326 DIGITAL SYSTEMS DESIGN II

LOADING OF LOGIC GATE

When output of a logic gate is connected to one or more input gate a load on the driving gate is created. There is a limit to
the number of load gate input that a given gate can drive. This limit is called the fan-out of a gate.
EENG 326 DIGITAL SYSTEMS DESIGN II

𝐼 (𝑚𝑎𝑥)
𝑓𝑎𝑛 − 𝑜𝑢𝑡 𝐻𝑖𝑔ℎ = | 𝑂𝐻(𝑚𝑎𝑥) |
𝐼𝐼𝐻

𝐼 (𝑚𝑎𝑥)
𝑓𝑎𝑛 − 𝑜𝑢𝑡 𝐻𝑖𝑔ℎ = | 𝑂𝐿(𝑚𝑎𝑥) |
𝐼𝐼𝐿

𝐹𝑎𝑛 − 𝑜𝑢𝑡 = 𝑤𝑜𝑟𝑠𝑡 𝑐𝑎𝑠𝑒

𝟏
𝒕𝒑𝒅 𝒂𝒗𝒈 = [𝒕𝑷𝑳𝑯 + 𝒕𝑷𝑯𝑳 ]
𝟐
𝟏
𝑨𝒗𝒆𝒓𝒂𝒈𝒆 𝒔𝒖𝒑𝒑𝒍𝒚 𝒄𝒖𝒓𝒓𝒆𝒏𝒕 = 𝑰𝑪𝑪(𝒂𝒗𝒈) = [𝑰 + 𝑰𝑪𝑪𝑳 ]
𝟐 𝑪𝑪𝑯

𝑨𝒗𝒆𝒓𝒂𝒈𝒆 𝒑𝒐𝒘𝒆𝒓 𝒅𝒊𝒔𝒔𝒊𝒑𝒂𝒕𝒊𝒐𝒏 = 𝑷𝑫 = 𝑰𝑪𝑪(𝒂𝒗𝒈) 𝑽𝑪𝑪

CLASSWORK SET
1. A certain draws 2uA when its output is high and 3.6uA when the output is low. What is its average power dissipation if
𝑉𝐶𝐶 = 5𝑉.
EENG 326 DIGITAL SYSTEMS DESIGN II

Methods of determining the loading of any digital circuit

Step 1:
Add up all the IIH for all input connected to output. This sum must be less than the output IOH Specification

∑ 𝑰𝑰𝑯 ≤ 𝑰𝑶𝑯

Step 2:
Add up all the IIL for all input connected to output. This sum must be less than the output IOL specification.

∑ 𝑰𝑰𝑳 ≤ 𝑰𝑶𝑳

Note: Negative sign only shows direction

EENG 326 DIGITAL SYSTEMS DESIGN II

CLASSWORK SET

1. A 74ALS00 NAND gate output drives 3(74S) gates input and 1(7406) input.
a. Determine if there is a loading problem.
b. If the 74ALS00 NAND gate in (a) needs to be used to drive some 74ALS input in addition to the load input
describe in (a). How many additional 74ALS input can the output drive without been overloaded?

2. How many 74LS input can typically be driven by 74HC output? Repeat for a 4000B output.
3. The datasheet for a quad two-input NAND gate specifies the following parameter:
𝐼𝑂𝐻 (𝑚𝑎𝑥) = 0.4𝑚𝐴, 𝐼𝑂𝐿 (𝑚𝑎𝑥) = 8𝑚𝐴, 𝐼𝐼𝐻 (𝑚𝑎𝑥) = 20𝜇𝐴, 𝐼𝐼𝐿 (𝑚𝑎𝑥) = 0.4𝑚𝐴, 𝑉𝑂𝐻 (𝑚𝑖𝑛) = 2.7𝑉, 𝑉𝐼𝐿 (𝑚𝑖𝑛) = 2𝑉,
𝑉𝑂𝐿 (𝑚𝑎𝑥) = 0.4𝑉, 𝑉𝐼𝐿 (𝑚𝑎𝑥) = 0.8𝑉 , 𝐼𝐶𝐶𝐻 (𝑚𝑎𝑥) = 1.6𝑚𝐴, 𝐼𝐶𝐶𝐿 (𝑚𝑎𝑥) = 4.4𝑚𝐴,
𝑡𝑃𝐿𝐻 = 𝑡𝑃𝐻𝐿 = 15𝑛𝑠 and a supply voltage of 5V.
Determine
a) The average power dissipation of a single gate
b) The maximum average propagation delay of a single gate
c) The high-state noise margin and
d) The low-state noise margin
e) How many gates input can be driven from the output of a NAND gate of this type?

4. A 74AC/74ACT gate is driven 20 74AS gate. If it is desired to drive some 74ALS in addition to this. Find the
maximum possible number of 74ALS gate which can be connected.
EENG 326 DIGITAL SYSTEMS DESIGN II

CIRCUIT HAZARDS
Hazards: They are unwanted switching transients that may appear at the output of digital circuit which will have a faulty
operation. They are temporary as the logic circuit will eventually settle to the desire functions.

Types of Hazards
1. Static Hazard
2. Dynamic Hazard
3. Functional Hazard
4. Essential Hazard

GENERATION OF SPIKES

But 𝐴. 𝐴̅ = 0 at all instances.

EENG 326 DIGITAL SYSTEMS DESIGN II

STATIC-0-HAZARD
EENG 326 DIGITAL SYSTEMS DESIGN II

OR GATE
EENG 326 DIGITAL SYSTEMS DESIGN II

NAND GATE
EENG 326 DIGITAL SYSTEMS DESIGN II

NOR GATE
EENG 326 DIGITAL SYSTEMS DESIGN II

1. STATIC HAZARD
• STATIC-0-HAZARD

Any circuit with Static 0 hazard must be reduced to the circuit if other variables are set to appropriate constant.
This deals with AND or NOR gates
Characteristics
1. Two parallel paths
2. One inverted
3. Reconverge to AND/NOR gate.
EENG 326 DIGITAL SYSTEMS DESIGN II

• STATIC-1-HAZARD

Any circuit with static-1-hazard must be reduced to the circuit above if other variables are set to appropriate constant.
This deals with OR and NAND gate.
Characteristics
1. Two parallel paths
2. One inverted
3. The converge to an OR/NAND gate.

Elimination of Static-1-Hazard
1. Plot the function on a k-map.
2. Test for static one hazard
3. Look for adjacent 1’s not covered by the same prime implicant.
4. Modify the function by the inclusion of the additional prime implicant.
5. Test the hazard free function with the same condition.
6. Draw the hazard free circuit. NB: Static-1-Hazard is applicable to NAND gate implementation and SOP equation.
EENG 326 DIGITAL SYSTEMS DESIGN II

Note: Static-0-hazard are applicable to product of sum (POS)

CLASSWORK SETS

1. Implement a hazard free circuit for the function. 𝐹 = 𝐴̅𝐵̅𝐶̅ + 𝐴̅𝐵𝐶̅ + 𝐴̅𝐵𝐶 + 𝐴𝐵𝐶

2. Identify and eliminate hazard in the function 𝐻(𝐴, 𝐵, 𝐶, 𝐷) = ( 𝐴̅ + 𝐶)( 𝐷

̅ + 𝐶)( 𝐶̅ + 𝐵)
EENG 326 DIGITAL SYSTEMS DESIGN II

DYNAMIC HAZARD
Dynamic hazard is said to exist when the output of a circuit changes two or more times when it should have change
once only in respond to an input change. This type of hazard occurs as a result of factorization or when a variable in a
logic circuit undergoes at least three-part delay. It manifests itself in an output which will normally make a 0 – 1 or 1-0
transition making a transition of 0-1-0-1 or 1-0-1-0 respectively.

Types of Dynamic Hazard

1. Dynamic Hazard with Embedded Static-0-hazard
Any circuit with dynamic hazard with embedded static-0-hazard must reduce to the equivalent circuit above if other
variables are set to appropriate constants.
EENG 326 DIGITAL SYSTEMS DESIGN II

2. Dynamic Hazard with Embedded Static-1-hazard

Any circuit with dynamic hazard with embedded static-1-hazard must reduce to the equivalent circuit above if
other variables are set to appropriate constants.

CLASSWORK SET
1. Identify all forms of hazards 𝐹(𝐴, 𝐵, 𝐶, 𝐷) = (𝐴 + 𝐵)(𝐵̅𝐶̅ + 𝐵𝐷
̅)
EENG 326 DIGITAL SYSTEMS DESIGN II