INDIAN INSTITUTE OF TECHNOLOGY BOMBAY
ELECTRICAL ENGINEERING DEPARTMENT
EE-Midsem
Monday Apr. 24, 2023 MS-101 Makerspace Marks: 40
Time: 15:15-16:00 Spring Semester 2022-23 (To be re-scaled)
Roll Number: Name:
Division: Batch: Signature:
Answer the following in the space provided with the questions.
Q–1 Circuit diagram of the op amp I to V converter used in Expt. 3 is shown below.
The device under test (DUT) is connected between terminals B and C.
Assume that the op amp is ideal.
+Vcc = +12 V, −Vcc = −12 V; R1 = 1 kΩ, RF = 2 kΩ.
Also assume that the maximum and minimum VOut levels are +Vcc and −Vcc respectively.
Calculation steps must be shown with your answer.
No marks will be awarded without proper steps.
A R1 B
VDUT
VIN IDUT DUT
RF IDUT
C
DUT choices 7 +VCC
2
6 +
3 VOut
Resistor Rectifier Zener LED
4 -
Diode Diode
-VCC
LM741 Op amp
a) A 1 kΩ resistor is connected as the DUT.
If VIN = +4 V, what will Steps
be the values of VDU T and
VOut ?
Answer: VDU T = V , VOut = V
– [2]
1
b) A Zener diode is connected as the DUT with its anode at terminal B and cathode
at terminal C. The Zener voltage is 3.2 V, and the Zener I-V characteristic is linear
in the Zener region with a slope of 200 Ω.
If VIN = −8 V, what will Steps
be the values of VDU T and
IDU T ?
Answer: VDU T = V , IDU T = mA
– [2]
c) An LED is connected as the DUT with its anode at terminal B and cathode at
terminal C. The LED cut-in voltage is 2.5 V (below this voltage the LED draws
negligible current).
If VIN = +2 V, what will Steps
be the values of VDU T and
VOut ?
Answer: VDU T = V , VOut = V
– [2]
– [Q1: 2+2+2=6 marks]
2
Q–2 Three blocks with their terminals, viz. Power supply, AFG and LM 741 op amp are
shown below.
Ch1 (12 V) Ch2 (12 V)
2 +VCC
7
6
CH-1 3 4
-VCC
+ + AFG
Signal LM 741
Power Supply Generator Op amp
Show the wiring between these three blocks so as to obtain a non-inverting amplifier
with a voltage gain of 16. (Add the connections to the diagram above).
Connect also the required resistors out of the following resistor values:
1 kΩ, 10 kΩ, 15 kΩ, 16 kΩ, 17 kΩ, 160 kΩ and 170 kΩ.
Assume that both Ch1 and Ch2 of Power supply are set at 12 V. You must use the
Power supply Ch1 as +VCC and Ch2 as −VCC . – [Q2: 5 marks]
Q–3 A digital circuit receives a natural number in the range 0 ≤ n ≤ 15 represented by 4 bits
ABCD (with A as the most significant bit). We want to design the logic for outputting
a ‘Select’ signal when n is any one of 0, 1, 2, 8, 9 or 10.
a) – [2]
Fill entries in the truth Answer:
table shown on the right for A B C D Select
‘Select’ as a function of A, 0 0 0 0
B, C and D. Be very care- 0 0 0 1
ful with these entries. 0 0 1 0
Errors in this part will 0 0 1 1
lead to wrong results in 0 1 0 0
the remaining parts! 0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
3
b)
Express ‘select’ in canonical Answer:
form as a sum of products.
– [2]
c)
Fill entries in the Karnaugh Answer:
map shown on the right for
‘Select’ as a function of A, AB→ 00 01 11 10
B, C and D. CD↓
00
01
11
10
Show the maximal group- Select =
ings of ‘1’s in the Kar-
naugh map above and de-
rive the minimal logic ex-
pression for ‘select in terms
of A,B,C,D and their com-
plements.
– [4]
– Q3: 2+2+4 = 8 marks
Q–4
We need to generate the Logic Diagram:
function:
f = (P + Q) · (R + S) from
input signals P, Q, R and S.
(Their complements are not
provided as inputs).
IC 7400 provides 4 2-input
NAND gates in a single
package. Implement the
function f using a single
7400 package (i.e. Using
4 or fewer 2-input NAND
gates).
– Q4: 5 marks
4
Q–5 Consider the circuit on the right using two
positive edge triggered JK flipflops. You are
given that at t=0, Q1 = Q2 = 0. J1 Q1 J2 Q2
K1
Ck1 K2 Ck2
Q1 Q2
Clock
Four positive clock edges ar-
rive after this initial state. Q1 Q2
What will be values of Q1 At t=0 0 0
and Q2 after the arrival of After Clock1
each of the clock edges? After Clock2
After Clock3
After Clock4
– Q5: 4 marks
Q–6 a) What is the least number of bits required to represent:
i) 128 (decimal) in unsigned binary format, Answer:
ii) +128 (decimal) in two’s complement signed format, Answer:
iii) −128 (decimal) in two’s complement signed format, Answer:
iv) +15 (decimal) in two’s complement signed format. Answer:
– [2]
b) i) Represent the unsigned number 1123 (decimal) in base 16 format (Hex code)
as a 12 bit wide quantity. Answer:
ii) Represent the same number (1123 decimal) in base 8 format (octal)
as a 12 bit wide quantity. Answer:
– [2]
c) What decimal signed number is represented by the 12 bit Hex number D28 if
we are using 2’s complement convention for signed numbers? Answer:
– [1]
– [Q6: 2 + 2 + 1 = 5 marks]
5
VCC = 5V
Q–7 Outputs of two open collector buffer gates are shorted
2.2K
as shown in the circuit diagram on the right. Waveforms Out
for the inputs applied to the two gates are shown below.
In1 In2
(Open collector buffers)
5V
In1 0V
5V
In2 0V
5V
Out 0V
Add the waveform at the terminal marked Out to the figure with the same time scale
as In1 and In2. – [Q7: 5marks]
Q–8
Find the voltage at nodes A and B in the
A
R R circuit shown on the left. The voltage source
B
provides 4V.
4V 2R 2R 2R Voltage at node A is: V
Voltage at node B is: V
– [Q8: 2 marks]
Paper Ends
Rough Work
