1026 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 49, NO.

5, OCTOBER 2002

New Feedforward Space-Vector PWM Method

to Obtain Balanced AC Output Voltages in a
Three-Level Neutral-Point-Clamped Converter
Josep Pou, Student Member, IEEE, Dushan Boroyevich, Member, IEEE, and Rafael Pindado, Member, IEEE

Abstract—In three-level neutral-point-clamped voltage-source capacitors must be confined to one-half the level of the dc-link
inverters, proper modulation allows the average voltages of the voltage to take full benefit of the converter. Springmeier et
dc-link capacitors to be kept at one-half the level of the dc-link al. [2] were some of the early contributors to deal with this
voltage. However, in some operating conditions, a low-frequency
ripple appears in the neutral-point potential and its frequency is balance problem in 1990 and several other publications discuss
three times that of the output voltages. As a result, the output volt- solutions [3]–[6]; however, this objective cannot be achieved
ages also have low-frequency distortion, which includes even and when operating with high modulation indexes, mainly when a
odd multiples of the fundamental. In this paper, a new space-vector low-power-factor load is connected [7]. Under such conditions,
pulsewidth-modulation strategy is presented to avoid that low-fre- the average value of the neutral-point (NP) current calculated
quency output voltage distortion. This modulation method tries to
balance the voltages of the capacitors by using only three vectors over a modulation period cannot be maintained at zero. There-
per modulation cycle. The duty ratios are directly calculated from fore, a low-frequency ripple in the NP potential appears, the
the space-vector diagram, even when balance is not achieved. For frequency of which is three times that of the output voltages. If
all cases, the result is a balanced set of three ac output voltages. the space-vector pulsewidth-modulation (SV-PWM) strategy
Some simulated and experimental results are given to validate the does not take into account this imbalance, the obtained output
method.
line-to-line voltages will contain even- and odd-order low-fre-
Index Terms—Compensated modulation, feedforward modula- quency harmonics. Obviously, these harmonics will degrade the
tion, multilevel inverter, neutral-point balance, space-vector mod- performance of the load, which is an important consideration
ulation, three-level inverter.
for some applications, such as ac motor drives or applications
in which the converter is connected to the electrical grid. A
I. INTRODUCTION solution has been proposed for sinusoidal PWM (SPWM) [8],
but this modulation does not have the benefits of the SV-PWM,
S INCE ITS introduction in 1981 [1], the three-level neu-
tral-point-clamped (NPC) voltage-source inverter (VSI)
has demonstrated some advantages over the conventional
such as larger output voltages and reduced switching frequency
of the devices. An SV-PWM approach for obtaining balanced
two-level inverter for high-power applications. Using the ac output voltages when the dc-link capacitors have a perma-
same dc-link voltage, the main advantages for the three-level nent voltage imbalance is presented in other work [9]. That
converter are that the maximum voltage applied to the devices approach requires four vectors for each modulation period
of the bridge is half the level of the dc-link voltage and the and their duty cycles are corrected after being calculated in a
spectrum of the output voltages is improved due to having balanced SV diagram.
one more available level. The drawbacks for this converter are In this paper, the proposed modulation method is based on ob-
that its topology and system control are more complicated. taining the duty cycles directly from the unbalanced SV diagram
Additionally, the voltages of the two series-connected dc-link and, therefore, requires no subsequent corrections. This process
takes advantage of symmetry in the unbalanced diagram to sim-
plify long operations so that the approach can be implemented
Manuscript received July 4, 2001; revised November 30, 2001. Abstract pub- in a real-time digital processor. Additionally, since only three
lished on the Internet July 15, 2002. This work was supported by the Departa-
ment d’Universitats, Recerca i Societat de la Informació of the Generalitat de
vectors are used during each modulation period, the switching
Catalunya, under Grant 2000BEAI200225. This work made use of ERC Shared frequencies of the devices are reduced.
Facilities supported by the National Science Foundation under Award Number
EEC-9731677.
J. Pou was with the Center for Power Electronics Systems (CPES), The II. BASIS OF THE METHOD
Bradley Department of Electrical and Computer Engineering, Virginia
Polytechnic Institute and State University, Blacksburg, VA 24061 USA, on
A. Balanced Vector Diagram
leave from the Department of Electronic Engineering, Universitat Politècnica The functional diagram of the three-level NPC converter
de Catalunya, 08222 Terrassa, Spain (e-mail: [email protected]).
D. Boroyevich is with the Center for Power Electronics Systems (CPES), is shown in Fig. 1(a). Assuming balanced dc-link capacitor
The Bradley Department of Electrical and Computer Engineering, Virginia voltages, the vector diagram in Fig. 1(b) is obtained when the
Polytechnic Institute and State University, Blacksburg, VA 24061 USA (e-mail: following transformation is applied to all combinations of the
[email protected]).
R. Pindado is with the Department of Electronic Engineering, Universitat output voltages:
Politècnica de Catalunya, 08222 Terrassa, Spain (e-mail: [email protected]).
Publisher Item Identifier 10.1109/TIE.2002.803207. (1)
0278-0046/02$17.00 © 2002 IEEE
POU et al.: NEW FEEDFORWARD SPACE-VECTOR PWM METHOD 1027

TABLE I
(A) SELECTION CRITERIA BETWEEN VECTORS 211 AND 100 AND VECTORS 221
AND 110 (B) EQUIVALENCES OF CURRENTS TO PROCESS CALCULATION
IN THE FIRST SEXTANT

(a)

(a)

(b)

Fig. 2. Some projections of the reference vector m~ (p~ and p~ ).

B. Criteria for the Selection of Short Vectors
Since only three vectors are used per modulation period in
this approach, a single short vector will be selected from each
(b) pair. The choice is made according to the objective of main-
Fig. 1. (a) Functional diagram of a three-level converter. (b) Space-vector taining balanced voltages in the dc-link capacitors; hence, the
diagram. present voltage imbalance and the direction of the instantaneous
output currents must be known [5]. The NP current ( ) must be
The diagram is divided into sextants and each sextant is then positive in order to discharge the lower capacitor and must be
divided into four regions in order to show the vectors nearest to negative to charge it. For example, if is positive, vector 100
the reference ( ), which must be generated for each modulation will discharge the lower capacitor ( ) and vector 211
period ( ). will charge it ( ).
The three vectors in the origin of the diagram (000, 111, Since all the modulation will be calculated in the first sextant,
222) connect all the outputs of the converter to the same dc-link this criterion can be expressed as shown in Table I(a). When
voltage level and, therefore, they do not produce any current in the reference vector lies in the first sextant, currents and
the dc side. The largest vectors of the diagram (200, 220, 020, in these tables will be and , respectively, but they must be
022, 002, 202) do not affect the voltage balance of the capaci- changed when it lies in another sextant. These equivalences are
tors, since they do not connect any output of the converter to the given in Table I(b).
NP. The medium vectors (210, 120, 021, 012, 102, 201) fix one
output to the NP; thus, the corresponding output current will C. Calculation of the Duty Cycles by Using Projections
define the NP current ( ). This connection produces voltage Any set of three vectors , and in a plane ( in Fig. 2)
imbalances in the capacitors, which must be compensated. The can generate any reference vector in the same plane using
short vectors of the diagram are double vectors, which means PWM-averaged approximation, if the reference vector lies in the
that two states of the converter can generate the same voltage triangle connecting the tips of , and . A general method
vector. As they affect the NP current in opposite ways, proper to calculate the duty cycles of these vectors is explained below.
utilization of these vectors will help the NP voltage achieve bal- The vectors and in Fig. 2 are the projections from the
ance. reference vector onto the segments that join the extreme of
1028 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 49, NO. 5, OCTOBER 2002

Fig. 4. Symmetries in the first sextant in the case of unbalanced voltages in

Fig. 3. Components gh from different reference vectors. Equivalences in the the dc-link capacitors (v > v ).
first sextant.

TABLE II
DETERMINATION OF THE SEXTANT FROM m AND m AND THEIR
EQUIVALENT COMPONENTS IN THE FIRST SEXTANT (m ; m )

to and to , respectively. Therefore, the vector can Fig. 5. Different projections of the reference vector in the normalized first
be expressed as follows: sextant.

(2)
or D. – Transformation
It is quite common for the control stage to provide the refer-
(3) ence vector in components. Transformation (7) is proposed to
translate these components directly into some very useful vari-
where and are the lengths of the vectors and , ables for the modulation
respectively. Finally, the reference vector can be expressed as
- with
(4)
From (4), the duty cycles of the vectors can be directly de- - (7)
duced as follows:
and (5) where is the coordinate reference angle.
Using this transformation, the control signals given in the or-
If the balanced vector diagram in Fig. 1(b) is normalized to
thogonal rotating coordinate frame ( components) are directly
have triangular regions with unity lengths ( ), the
translated into a nonorthogonal base in the stationary coordinate
calculation of those duty cycles is simplified as
frame ( components). In fact, the new reference axes are the
and (6) ones that limit the first sextant and which are separated by 60 .
When dealing with the unbalanced case, these lengths can no The value of the coefficient in (7) must be defined so that in the
longer be considered to be unity because they change according new axes the SV diagram is fitted into a two-unit-side hexagon.
to the present imbalance. In that case, (5) must be applied. This coefficient depends on which sort of variables (phase or
POU et al.: NEW FEEDFORWARD SPACE-VECTOR PWM METHOD 1029

TABLE III
REGION SET CONDITION AND DUTY-CYCLE CALCULATION

line-to-line) are processed for the control and also on the coef- dealing with phase variables, the parameter must be unity.
ficient used for the transformation. For example, when using When line-to-line variables are used for the control, must be
power conservative transformation (coefficient ) and .
1030 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 49, NO. 5, OCTOBER 2002

From the values and , the sextant where the reference TABLE IV
vector lies can be directly found, as can the components of the INTERCHANGES OF THE OUTPUT STATES DEPENDING ON THE SEXTANT
IN WHICH THE REFERENCE VECTOR LIES (AFTER PROCESSING
equivalent vector in the first sextant and . These relation- CALCULATION IN THE FIRST SEXTANT)
ships are illustrated in Fig. 3 and Table II.

III. UNBALANCED CASE

Several vectors of the SV diagram are affected when the volt-
ages of the dc-link capacitors are not equal. The short double
vectors are split and can, therefore, no longer be considered as only one case per region and therefore, only four cases must be
only one voltage vector. One of them becomes smaller and the considered for any modulation cycle.
other larger, according to the direction of the imbalance, while It is important to mention the following points.
the sum of both vectors remains constant. On the other hand, the • Although the shapes of the regions are not equilateral tri-
medium vectors not only change in length but also in phase, so angles, each still retains at least one s60 angle that is used
that their tips follow the boundary of the external hexagon. Fig. 4 as a center for vector decomposition.
shows the representation of the first sextant when the voltage of • Regions 1, 3, and 4 are activated when the only duty cycle
the lower capacitor is higher than the upper one. Despite the able to potentially be negative is instead positive. The ac-
imbalance, the shape of this sextant still remains a regular tri- tivation of Region 2 hinges on the nonactivation of the
angle; additionally, the changes produced in the vectors are not others. Therefore, only at most three simple comparison
at random, but instead follow symmetries. All these changes operations must be done to determinate the appropriate re-
must be taken into account when an accurate reference vector gion.
is required; thus, the modulation stage must sense both voltages • The case “Region 2 (100–221)” cannot be analyzed by
from the capacitors in order to establish a proper feedforward symmetries. Therefore, it has been calculated analytically.
control. Since this case and the case “Region 4 (100–221)” will
Parameters and are defined to reveal the modulation require more switching steps for the switches of the con-
process under unbalanced conditions verter, they could be ignored in the modulation. Instead,
either to replace vector 100 with 211 or vector 221 with
and (8) 110 can be considered. For example, if vector 100 is sub-
stituted for vector 211, the case “Region 2 (100–221)”
becomes the case “Region 2 (211–221).” The process is
which can be related to each other as similar for Region 4. Nevertheless, in order to not lose
much control for the NP balance, the expressions
(9) and would be helpful in de-
ciding which change should be done, such that the highest
The complicating factor is that the regions change their value reveals which vector has more influence on the bal-
shapes and are also dependent on which short vectors are ance (100 or 221, respectively). These expressions are rea-
selected for each modulation cycle. Therefore, it seems quite soned from the standpoint that the closer and are
difficult to determine in which region lies the extreme of the to the unity value, the higher will be the control of the NP
reference vector and also, to work out the duty cycles for the voltage. Obviously, the phase current levels also directly
vectors. Nevertheless, as all the regions still keep at least one affect such control.
• To process faster the values given in Table III by a digital
60 angle, the components and will be very useful for
signal processor (DSP), parameters and can be
both processes. However, first, it is necessary to define a new
calculated previously by a division algorithm, so that only
variable that depends on them, as follows:
product operations remain to be applied.
(10) After determining which sequence best enables the vectors
in the first sextant to achieve low switching frequency, the next
Graphically, these parameters can be represented in the nor- and final step is to apply the calculated duty cycles to the corre-
malized first sextant (Fig. 5). sponding vectors. This task requires the knowledge of the real
Table III shows all possible cases, as well as duty cycles, sextant in which the reference vector lies and it can be performed
by simply interchanging the states of the output phases in accor-
which have been calculated by the method of projections
dance with the equivalences given in Table IV.
discussed in Section II-C. There are 12 cases that have been
grouped into four sets, in accordance with the regions defined
in Fig. 1(b). For example, since Region 1 uses only one short IV. SIMULATED RESULTS
vector, there are two cases for this region, “Region 1 (100)” and Some simulated results are obtained from Matlab-Simulink.
“Region 1 (211),” depending on the selected short vector. For For this example, the converter shown in Fig. 1(a) is supplied by
Region 3, the situation is similar with vectors 110 and 221. On a dc source V and the output currents are provided
the other hand, as Regions 2 and 4 use two short vectors, each by a balanced set of three-phase current sources with an rms
has four cases. Once the short vectors are selected according value A and a frequency Hz. The dc-link
to the balance requirements, the modulation process deals with capacitors are F and the amplitude of the normalized
POU et al.: NEW FEEDFORWARD SPACE-VECTOR PWM METHOD 1031

(a) (b)
Fig. 6. Average model simulations for some different load current angles ('). (a) Without feedforward compensation. (b) With feedforward compensation.

reference vector is (100%), which is the worst case for ters and are defined to be unity; hence, a balanced SV dia-
producing voltage oscillations in the NP. None of the possible gram is assumed for the calculation of duty cycles. The selection
cases listed in Table III have been excluded from the modulation of the short vectors for the NP voltage balance compensation is
process. also applied (Table I). Low-frequency distortion appears in the
The results shown in Fig. 6 include the voltage of the lower output voltages for these cases when the amplitude of the NP
capacitor ( ) as well as the ac output line-to-line voltages; all voltage ripple becomes significant. In contrast, the output volt-
of these are local average variables in order to distinguish the ages obtained by the feedforward modulation are perfectly bal-
quality of the waves obtained by the proposed modulation. Dif- anced and have no distortion.
ferent load-phase-current angles ( ) have been considered for The amplitude of the NP voltage ripple for load angles
the simulations. For the noncompensated method, the parame- is smaller for the feedforward modulation algorithm.
1032 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 49, NO. 5, OCTOBER 2002

Fig. 7. Voltage ripple in the NP for different phase current angles ('). Discontinuous lines: no compensated method; continuous lines: with feedforward
compensation.

(a) (b)
Fig. 8. DC-link voltages (v ;v ), filtered line-to-line voltage (v ), and output phase current (i ). (a) No compensation. (b) With feedforward modulation.

However, this voltage amplitude is bigger for load angles length of the reference vector), it can be used for purposes of
. design. Therefore, going through this graphic, the maximum
The normalized NP peak-to-peak voltage ripple is graphically voltage applied to the capacitors and the devices of the bridge
quantified in Fig. 7 ( ), in which all the curves illustrated are can be calculated as follows:
for constant values of the nondimensional parameter , which
is defined as follows: (12)

(11) Nevertheless, when the system behaves as a rectifier (the en-

ergy flows from the ac side to the dc side), the ripple is not al-
This figure shows that reactive components of the output cur- ways centered at a value half the level of the dc-link voltage.
rents produce more voltage imbalance in the NP. As the infor- This does not happen when operating with unity power factor
mation given is for the worst operation conditions (maximum ( ), but does occur at some nearby operating points.
POU et al.: NEW FEEDFORWARD SPACE-VECTOR PWM METHOD 1033

(a)

(b)
Fig. 9. Experimental and simulated results with significant NP voltage ripple. (a) No compensation. (b) With feedforward modulation.

Some instabilities of the system were also reported [8] for the cycles of the short vectors are sufficiently large. Further insight
SPWM feedforward method. into this phenomenon might be gained in future work.
This behavior of the converter can be explained as follows.
When the modulation algorithm assumes a balanced SV di- V. EXPERIMENTAL RESULTS
agram, the average value of the NP current produced by the
medium vectors and calculated over a line period is zero. In The feedforward modulation algorithm has been pro-
contrast, this does not happen with the feedforward modula- grammed in a 32-bit floating-point digital processor (Sharc
tion. However, their effect can usually be compensated for by ADSP 21 062) with 25-ns instruction processing time. Since the
proper utilization of the short vectors. The problem appears for algorithm requires less than 6 s to be processed, it was applied
to a three-level converter with modulation period s.
very large modulation indices, when the duty cycles of the short
Fig. 8 shows the voltages of the two dc-link capacitors, a low-
vectors are very small. It seems that when the converter is oper-
pass-filtered line-to-line output voltage, and an output phase
ating as a rectifier, there are some current phase conditions that
current. An asynchronous motor is connected as a load and the
render the NP current contribution of the short vectors insuf-
capacitors are forced to have a permanent voltage imbalance
ficient to compensate the imbalance generated by the medium by means of two dc power supplies. The upper one is adjusted
vectors. Thus, the NP voltage exhibits an offset, which can be to 60 V and the lower one to 10 V. When the NP connection
positive or negative. However, this new stable point might not is released, the modulation process itself controls the voltage
be achieved depending on the transition process and the initial balance. As the selection of the dual vectors is properly made,
conditions of the NP voltage. Then, the system might collapse the balance is achieved. The line-to-line output voltage and the
in such a way that the full dc-link voltage is applied to only one output current are not affected during this dynamic process,
capacitor. Although the feedforward modulation can still gen- thanks to the feedforward modulation.
erate a balanced set of ac output voltages in such conditions, the In Fig. 9, the total dc-link voltage is 60 V, the amplitude
devices of the bridge and one of the capacitors would support of the reference vector (95%), and the funda-
too much voltage to maintain the system operating. mental output frequency is 10 Hz. This low frequency is de-
From numerous simulations, it seems that the instability fined to achieve significant NP voltage oscillation ( ). The
problem in the rectifier mode can be avoided if the modulation rms output phase current in such conditions is A, with
index is limited below (90%), so that the duty angle . The line-to-line output voltages shown in this
1034 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 49, NO. 5, OCTOBER 2002

figure are also refined by a first-order low-pass filter. These volt- Josep Pou (S’97) received the B.S. and M.S. degrees
ages have low-frequency distortion when the feedforward mod- in 1989 and 1996, respectively, from the Universitat
Politècnica de Catalunya (UPC), Terrassa, Spain,
ulation is not used, whereas the waveforms are practically si- where he is currently working toward the Ph.D.
nusoidal when it is applied. These experimental results are also degree in the Department of Electronic Engineering.
verified by simulations. During 1989, he was the Technical Director of
Polylux S.A. In 1990, he joined the faculty of UPC
as an Assistant Professor. He became an Associate
VI. CONCLUSION Professor in 1993. From February 2001 to January
2002, he was a Researcher in the Center for Power
Using the SV-PWM method proposed in this paper, the op- Electronics Systems, Virginia Polytechnic Institute
erating area for the NPC three-level converter can be extended and State University, Blacksburg. His research interests include modeling and
to deep modulation indices and low-power-factor loads while control of power converters, motor drives, multilevel converters, and power
quality. He has authored more than 30 published technical papers and has been
avoiding any low-frequency distortion at the output voltages. involved in several industrial projects and educational programs in the fields of
Thus, the third harmonic oscillation in the NP voltage, which power electronics and systems.
appears in those conditions, no longer affects the output volt- Mr. Pou is a student member of the IEEE Industrial Electronics, IEEE Power
Electronics, and IEEE Industry Applications Societies.
ages and currents. Additionally, no other reason for imbalance in
the NP voltage will affect the output voltages when the feedfor-
ward modulation is applied. Furthermore, the whole modulation
process can be implemented in a DSP operating in real time be-
Dushan Boroyevich (M’82) received the B.S.
cause it is mainly based on comparison operations and products. degree from the University of Belgrade, Belgrade,
As this modulation algorithm requires short processing time, it Yugoslavia, in 1976, the M.S. degree from the Uni-
has been successfully applied in a converter operating at 20-kHz versity of Novi Sad, Novi Sad, Yugoslavia, in 1982,
and the Ph.D. degree from Virginia Polytechnic
switching frequency. Institute and State University, Blacksburg, in 1986.
Since the imbalance in the NP does not affect the output vari- Between 1986–1990, he was an Assistant Pro-
ables, the value of the dc-link capacitors can be greatly reduced. fessor and Director of the Power and Industrial
Electronics Research Program in the Institute for
However, as the amplitude of that oscillation increases, there is Power and Electronic Engineering, University
a corresponding increase in the maximum voltage that the de- of Novi Sad. He was later the Acting Head of
vices and the capacitors themselves must support, and so there the Institute. In 1990, he joined The Bradley Department of Electrical and
Computer Engineering, Virginia Polytechnic Institute and State University, as
is a tradeoff in the selection of the values of the capacitors. an Associate Professor. From 1996 to 1998, he was Associate Director of the
When the system operates as a rectifier with the feedforward Virginia Power Electronics Center and, since 1998, he has been the Deputy
modulation, some NP voltage offset appears, which can degen- Director of the NSF Engineering Research Center for Power Electronics Sys-
tems and a Professor in The Bradley Department of Electrical and Computer
erate into instability. The origin of this problem is justified and Engineering. His research interests include multiphase power conversion,
a solution is proposed, based on limiting the maximum modu- high-power PWM converters, modeling and control of power converters,
lation index for those operating conditions. applied digital control, and electrical drives. He has authored more than 100
published technical papers, is the holder of three patents, and has been involved
in numerous government and industry-sponsored projects in the areas of power
REFERENCES and industrial electronics.
Dr. Boroyevich is a member of the IEEE Power Electronics Society AdCom,
[1] A. Nabae, I. Takahashi, and H. Akagi, “A new neutral-point-clamped the Industrial Power Converter Committee of the IEEE Industry Applications
PWM inverter,” IEEE Trans. Ind. Applicat., vol. IA-17, pp. 518–523, Society, and Phi Kappa Phi.
Sept./Oct. 1981.
[2] F. Springmeier and J. Steinke, “Control of the DC-link neutral potential
of a three-level GTO inverter as a part of the direct self control (DSC),”
in Proc. PEMC’90, vol. 2, Budapest, Hungary, 1990, pp. 479–483.
[3] C. Newton and M. Sumner, “Neutral point control for multi-level
inverters: Theory, design and operational limitations,” in Conf. Rec. Rafael Pindado (M’94) received the B.Sc. degree in
IEEE-IAS Annu. Meeting, vol. 2, 1997, pp. 1336–1343. mechanical engineering from the EUETI, Barcelona,
[4] Y. H. Lee, B. S. Suh, C. H. Choi, and D. S. Hyun, “A new neutral point Spain, in 1961, the B.Sc. degree in electrical
current control for a 3-level converter/inverter pair system,” in Proc. engineering from the EUETI, Terrassa, Spain,
IEEE IECON’99, vol. 3, Oct. 1999, pp. 1528–1534. in 1966, and the M.Sc. and Ph.D. degrees, with
[5] L. Wei, Y. Wu, C. Li, H. Wang, S. Liu, and F. Li, “A novel space vector honors, in electrical engineering from the Universitat
control of three-level PWM converter,” in Proc. PEDS, vol. 2, July 1999, Politècnica de Catalunya (UPC), Terrassa, Spain, in
pp. 745–750. 1967 and 1990, respectively.
[6] S. Fukuda, Y. Matsumoto, and A. Sagawa, “Optimal-regulator-based He is currently a Professor in the Department of
control of NPC boost rectifiers for unity power factor and reduced neu- Electronic Engineering, UPC. Since 1967, he has
tral-point-potential variations,” IEEE Trans. Ind. Electron., vol. 46, pp. taught courses on control theory, analog electronics,
527–534, June 1999. and power electronics. His research interests include power quality, reactive
[7] N. Celanovic and D. Boroyevich, “A comprehensive study of neutral- power compensation, and harmonic elimination techniques applied to power
point voltage balancing problem in three-level neutral-point-clamped converters, modeling, and control of power electronics systems. Since 1998,
voltage source PWM inverters,” IEEE Trans. Power Electron., vol. 15, he has been the Director of the EUETI-Terrassa (UPC). He has authored
pp. 242–249, Mar. 2000. four technical books, more than 70 technical papers, and has been involved
[8] N. Celanovic, I. Celanovic, and D. Boroyevich, “The feedforward in several government and private company projects in the areas of control
method of controlling three-level diode clamped converters with small systems and power electronics. He was the General Chairman of the SAAEI
DC-link capacitors,” in Proc. IEEE PESC, vol. 3, June 2001, pp. 2000 Congress.
1357–1362. Dr. Pindado is a member of the IEEE Industrial Electronics and IEEE Power
[9] J. H. Seo and C. H. Choi, “Compensation for the neutral-point potential Electronics Societies. He was a Session Chairman of the 1999 IEEE Interna-
variation in three-level space vector PWM,” in Proc. IEEE APEC, vol. tional Symposium on Industrial Electronics. He was granted by the Ministerio
2, Mar. 2001, pp. 1135–1140. de Educación Nacional, Spain, for the academic years 1956–1966.