CMOS
Manufacturing
Process
Digital Integrated Circuits Manufacturing Process EE141
CMOS Process
Digital Integrated Circuits Manufacturing Process EE141
1
Circuit Under Design
VDD VDD
M2
M4
Vin Vout Vout2
M1 M3
This two-inverter circuit (of Figure 3.25 in the text) will be
manufactured in a twin-well process.
Digital Integrated Circuits Manufacturing Process EE141
Circuit Layout
Digital Integrated Circuits Manufacturing Process EE141
2
The Manufacturing Process
For a great tour through the process and its different steps, check
http://www.fullman.com/semiconductors/semiconductors.html
Digital Integrated Circuits Manufacturing Process EE141
Digital Integrated Circuits Manufacturing Process EE141
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Digital Integrated Circuits Manufacturing Process EE141
Process Flow
These slides only present only a couple of snapshots of the
manufacturing process for the circuits presented in the textbook.
For a complete overview of all 62 steps, please refer to:
http://tanqueray.eecs.berkeley.edu/~ehab/inv.html.
Credits for these pictures go to Ehab Hakeem, Prof. Andrew Neureuther
and the Simpl program.
Digital Integrated Circuits Manufacturing Process EE141
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Start Material
A
Starting wafer: n-type with
A’ doping level = 10 13 /cm3
* Cross-sections will be
shown along vertical line A-A’
Digital Integrated Circuits Manufacturing Process EE141
N-well Construction
(1) Oxidize wafer
(2) Deposit silicon nitride
(3) Deposit photoresist
Digital Integrated Circuits Manufacturing Process EE141
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N-well Construction
(4) Expose resist using n-well
mask
Digital Integrated Circuits Manufacturing Process EE141
N-well Construction
(5) Develop resist
(6) Etch nitride and
(7) Grow thick oxide
Digital Integrated Circuits Manufacturing Process EE141
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N-well Construction
(8) Implant n-dopants (phosphorus)
(up to 1.5 µm deep)
Digital Integrated Circuits Manufacturing Process EE141
P-well Construction
Repeat previous steps
Digital Integrated Circuits Manufacturing Process EE141
7
Grow Gate Oxide
0.055 µm thin
Digital Integrated Circuits Manufacturing Process EE141
Grow Thick Field Oxide
0.9 µm thick
Uses Active Area mask
Is followed by
threshold-adjusting implants
Digital Integrated Circuits Manufacturing Process EE141
8
Polysilicon layer
Digital Integrated Circuits Manufacturing Process EE141
Source-Drain Implants
n+ source-drain implant
(using n+ select mask)
Digital Integrated Circuits Manufacturing Process EE141
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Source-Drain Implants
p+ source-drain implant
(using p+ select mask)
Digital Integrated Circuits Manufacturing Process EE141
Contact-Hole Definition
(1) Deposit inter-level
dielectric (SiO2) — 0.75 µm
(2) Define contact opening
using contact mask
Digital Integrated Circuits Manufacturing Process EE141
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Aluminum-1 Layer
Aluminum evaporated
(0.8 µm thick)
followed by other metal
layers and glass
Digital Integrated Circuits Manufacturing Process EE141
Advanced Metalization
Digital Integrated Circuits Manufacturing Process EE141
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Design Rules
Jan M. Rabaey
Digital Integrated Circuits Manufacturing Process EE141
Cross-Section of CMOS Technology
Digital Integrated Circuits Manufacturing Process EE141
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Design Rules
l Interface between designer and process
engineer
l Guidelines for constructing process masks
l Unit dimension: Minimum line width
» scalable design rules: lambda parameter
» absolute dimensions (micron rules)
Digital Integrated Circuits Manufacturing Process EE141
CMOS Process Layers
Layer Color Representation
Well (p,n) Yellow
Active Area (n+,p+) Green
Select (p+,n+) Green
Polysilicon Red
Metal1 Blue
Metal2 Magenta
Contact To Poly Black
Contact To Diffusion Black
Via Black
Digital Integrated Circuits Manufacturing Process EE141
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Intra-Layer Design Rules
Same Potential Different Potential
9 2
0
Well or Polysilicon
6
10 2
3 3
Active Metal1
Contact
or Via 2
3 Hole 3
2 2 4
Select Metal2
Digital Integrated Circuits Manufacturing Process EE141
Transistor Layout
Transistor
3 2
Digital Integrated Circuits Manufacturing Process EE141
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Via’s and Contacts
2
4
Via
1 1
5
Metal to
Metal to 1 Poly Contact
Active Contact 3 2
2
2
Digital Integrated Circuits Manufacturing Process EE141
Select Layer
2
Select
3
2
1
3 3
2 5
Well
Substrate
Digital Integrated Circuits Manufacturing Process EE141
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CMOS Inverter Layout
GND In VDD
A A’
Out
(a) Layout
A A’
n
p-substrate Field
n+ p+ Oxide
(b) Cross-Section along A-A’
Digital Integrated Circuits Manufacturing Process EE141
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