Timepix4: Specs & Plans
X. Llopart
1
Timepix3 Timepix4
Timepix3 Timepix4
Technology IBM 130nm TSMC 65nm
Pixel Size 55 x 55 µm ≤ 55 x 55 µm
3-side buttable 4-side buttable
Pixel arrangement
256 x 256 256 x 256 or bigger
Data driven PC (10-bit) and TOT (14-bit) CRW: PC and iTOT (12...16-bit)
Operating Modes
Frame based TOT and TOA
Zero-Suppressed Data driven < 80 MHits/s < 500 MHits/s
Readout Frame based YES YES
TOT energy resolution < 2KeV < 1Kev
Time resolution 1.56ns ~200ps
Readout bandwidth 5.12Gb (8x SLVS@640 Gbps) 20.48 Gbps (4x 5.12 Gbps)
No volcano Dynamic gain
Front-end “with” Volcano
But supply only 1.2V
2
TOT High Resolution
Tpeak < 25ns
Preamp Out
Disc Out
Pixel Readout Starts
Clk (40MHz) (475ns→ 19 clock cycles)
Global TOA (14-bit) 16382 16383 16384 0 1 2 3 4
FTOA_rise (4 bits)=7 FTOA_fall (4 bits)=11
VCO Clk (640MHz)
TOA (14-bit) X 16383 TOA (14 bits)=16383
TOT (10 bits) =4
TOT Clk (40MHz)
TOT_ HiRes=(TOT) + FTOA_rise - FTOA_fall
3
Simulation
900
800
TOT (Timepix3) measured
700 TOT (Timepix3) simulated
TOT resolution [e- FWHM]
TOT (Timepix4) simulated
600
500
400
300
200
100
0
0 100 200 300 400 500 600
FE return to zero [ns/1ke-]
4
Timepix4
• Improve TOA resolution Latching of internal VCO phase
• Technique used by “Time-of-Flight 3D Imaging based on a SPAD-TDC Pixel
Arrays” ~25 ps resolution
5
TPIX4 VCO
• Improve TOA resolution Latching of internal VCO phase
• 5-tap VCO has 10 unique phases
• TOA reconstructed from:
1) TOA @ 40MHz (N-bits) tbd stage Phase[4] Phase[3] Phase[2] Phase[1] Phase[0]
2) FTOA @ 640MHz (4-bits) Init 10 1 0 1 0 1
(Enable=0) 1 1 0 1 0 0
3) UFTOA @ 6400MHz (4-bits)
2 1 0 1 1 0
3 1 0 0 1 0
4 1 1 0 1 0
5 0 1 0 1 0
6 0 1 0 1 1
7 0 1 0 0 1
8 0 1 1 0 1
9 0 0 1 0 1
Vcntr
VDD
Enable
NAND
Phase[0] Phase[1] Phase[2] Phase[3] Phase[4]
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Possible approach for Timepix4: DLL
N+1
Control the phases that arrive in the super
N
N+2 pixels of a double column using a voltage-
controlled delay line tuned by a delay-locked
N+3
loop (DLL)
N-1
In lock, Td = Tref/2N, i.e., the buffers’ delays, Td,
2N-2
are a well-defined fraction of the reference
4
clock (can be calibrated offline)
Robust to PVT variations in a first-order analysis
3
2N-1
The possibility of using a single PD/CP/LF for
the whole matrix is under investigation
2N Power and area benefits
2
We are also investigating the possibility of
implementing the control loop in the digital
1
domain
Phase Charge Pump &
Detector Loop Filter
Scalable and easily portable to more advanced
CKref Vctrl technology nodes
7
Timepix4 (also) as a photon counting chip?
• CRW (Continuous Read-Write):
• Packet based and zero-suppressed
• 2 x 12..16 bit counters per pixel:
• PC / PC
• iTOT / iTOT
• Possible operation modes:
• Controlled by external pin (as in Medipix3)
• Data controlled Data packet is generated after counter reaches
an on-pixel programmed value
• Single counter:
• Packet based and zero-suppressed
• 24..32 bit PC or iTOT
• Auto Threshold Calibration?
• On-pixel gain (TOT) calibration?
8
Timepix4 arrangement
26 mm
24.2 mm
Timepix3
Timepix4
256 x 256 pixels
1 superpixel 2x4 pixels 55um x 55um
220x64 superpixels (65 Kpixels)
436 x 581 pixels
32 mm
28.16 mm
55µm x 55µm x1
(253316 pixels)
440 x 512 pixels
55µm x 55µm
(225280 pixels)
x3.86 x3.4
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Large Timepix4:
TSV (4-side buttable) vs WireBonds (2-side buttable)
24.2 mm 24.2 mm
Timepix4-WB Timepix4-TSV
1 superpixel 2x4 pixels 1 superpixel 2x4 pixels
220x64 superpixels 220x64 superpixels
28.16 mm
30.16 mm
440 x 512 pixels 440 x 512 pixels
55µm x 55µm 55µm x 55µm
(225280 pixels) (225280 pixels)
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64B/66B encoding
• IEEE 802.3ae-2002 amendment which introduced 10 Gbit/s
Ethernet
• 3.125% bandwidth overhead
• Timepix3 25% in 8b/10b
• 64 bit event data (scrambled)
• Timepix3 48 bit (25% less)
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Data Packet in Event Data Driven
Timepix3 Timepix4
Event Data bits 48 64
Status 4 4
Address 16 65536 pixels 18 225280 pixels
TOA 14 409.6 µs @40MHz 18 6.55 ms @40MHz
FTOAr 4 1.5625 ns 4 1.5625 ns
FTOAf - 4 1.5625 ns
UFTOA - 4 ~200ps
TOT 10 12
Status[63:60] Address[59:42] TOA[41:24] UFTOA[23:20] FTOAR[19:16] FTOAF[15:12] TOT[11:0]
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Serializer1
Readout
Digital readout
Digital readout
1 2
& configuration
Analog biasing
• Readout (based in a 40MHz clock): Analog Periphery
• (Fast) 2x 5.12Gbps serializers:
Digital readout
Digital readout
• One on each digital domain 3 4
• 2.56Gbps, 1.28Gbps also available
• 64b/66b encoding
• (Slow) 2x 640Mbps SLVS drivers: Serializer2
• One on each digital domain
• 320Mbps, 160 Mbps, 80 Mbps and 40 Mbps also available
• 64b/66b encoding
• Slow Control:
• SPI bus addressing up to 80MHz:
• Control operation
• Write and Read registers
• Write and read pixel configuration
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Readout Rates
Timepix3 Timepix4
Readout Bandwitdh Up to 5.12 Gbps Up to 20.48 Gbps
Links x8 LVDS x4 CMOS serializers
Encoding 8b/10b 64b/66b
Number bits in full frame > 3.9 Mbits > 14.8 Mbits
Readout full Frame 768 µs 726 µs
Maximum chip hit rate 85.3 Mhits/s 310.3 Mhits/s
Maximum hit rate area 43.0 Mhits/s/cm2 45.5 Mhits/s/cm2
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Plans
• Original Plan was submit Medipix4 and Timepix4 simultaneously on the
same reticle
• Large Timepix4 is a recent proposal Not approved by collaboration:
• The photon counting (Synchrotrons…) requires a fast frame readout mode
• Studies on different key blocks already started:
• Pixel input RDL (Edinei/Xavi)
• Re-shaping of IP blocks to fit narrow layout constraints (Viros)
• DLL clock distribution (Edinei)
• On-pixel VCO and serializers (Nikhef)
• Medipix4 will come later maybe in 130nm
• Designers team from CERN and NIKHEF
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Conclusions
• Proposal for Timepix4:
• Particle tracking:
• ~200ps TOA
• ~1KeV FWHM TOT resolution
• Photon counting (deadtime ~300ns@20Kev):
• 1 counter 24..32 bits
• 2x counter 12..16bits in CRW zero supressed
• 1 threshold with 5-bits threshold tuning
• >500 e- minimum threshold
• Maybe: Auto threshold calibration and/or ToT gain tunning
• 4-side buttable
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