Fix bug where one-bit struct output ports improperly slice #629
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Description & Motivation
There was a bug where if you have a
LogicStructurewith total width of 1-bit, then do anaddTypedOutputon that struct, then assign the output, you could get something in generated SystemVerilog likeassign myOut[0] = ...even thoughmyOutwould only be 1-bit. This is illegal in SystemVerilog.This PR fixes the bug and adds tests to cover it. Also added a paranoia test on the
BusSubsetbut that one was already covered.Related Issue(s)
N/A
Testing
Added tests
Backwards-compatibility
No
Documentation
No